Principal Layout Designer at Micron Technology in Hyderabad, Telangana, India

Job description

• Our vision is to transform how the world uses information to enrich life for all.
• Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities

• You will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of Array, Digital and Analog circuits.
• You must execute secondary layout tasks such as ECO, LCO and DFM.
• You will be responsible for coordinating with TD, Design, CAD and layout teams to deliver on schedule with quality.
• You must demonstrate a strong ability to debug problems, find effective solutions, and negotiate with the engineering staff. You will be required to meet all engineering and process related criteria needed for an assigned NAND product.
• You will organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution.
• You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tape-out processes and procedures.
• You should be able to mentor Junior team members.
• You must drive innovation into the future Memory generations within a dynamic work environment.

Requirements

• As a Principal Layout Designer (10+ years of experience in layout)
• You must have the ability to understand design constraints and implement high-quality layouts.
• You must be proficient using Cadence VXL on periphery blocks.
• You must have strong debug and problem-solving skills for LVS, DRC & Layout issues.
• You must have hands-on experience in creating layout of critical Core/Pitch blocks such as Array, Row decoder & Column Decoder.
• You must have good understanding of Core/Pitch Layout fundamentals such as BL & WL pitch, and a feasibility acumen for developing WL & BL drivers & pre-drivers.
• You must have good experience of Chip Level Integration and Die Size calculations.
• You must have a good understanding of the Design rules and deliver with quality layout.
• You must deliver major level blocks, including signal and floorplan, to the Core/Pitch and Periphery area.
• Multiple Tape out support experience will be an added advantage.
• You must have a good understanding of automation and leveraging AI tool proficiency to enable your work.

Skills

Required

• Cadence VXL
• LVS, DRC & Layout debugging
• Layout design
• Chip level integration
• Die size calculations
• Design rules understanding
• ECO, LCO, DFM
• Automation and AI tool proficiency

Preferred

• Multiple tape out support experience