Systems Engineering Integration & Test Engineer - TIDES FPGA (PIE) at General Dynamics Mission Systems in Arizona

Responsibilities

• Systems Engineering Integration & Test Engineer - TIDES FPGA (PIE)
• As a Systems Engineering Integration & Test Engineer - TIDES FPGA, you will be a member of the Payload Integration and Evolution (PIE) team within SEIT’s organization. The PIE team develops and evolves the Payload Verification Platform (PVP), a hardware development environment made up of COTS and custom FPGA boards, development kits, and supporting infrastructure used to emulate spacecraft payload behavior for early integration, risk reduction, and test software development. In this role, you will support FPGA design, RTL development, simulation, interface integration, and lab bring-up for the PVP. Your work will help bridge test equipment with units under test, enable real-time functions such as packet timestamping and precision command scheduling, and mature the platform as payload programs move from early development toward verification and flight readiness.
• Support the Payload Integration and Evolution (PIE) team within SEIT’s TIDES organization in developing and maturing the Payload Verification Platform (PVP)
• Help integrate COTS and custom FPGA boards, development kits, test equipment, and payload hardware into a shared hardware development environment
• Support early payload emulation, interface testing, hardware bring-up, and risk reduction activities
• Work with systems, electrical, software, test, and FPGA engineers to understand integration needs and translate them into test platform capabilities
• Assist with FPGA development tasks such as RTL updates, simulation, interface checkout, and lab validation under guidance from experienced engineers
• Support real-time test functions such as interface bridging, packet timestamping, command scheduling, and payload communication emulation
• Debug integration issues using lab equipment, software tools, waveform captures, and structured engineering investigation
• Document test setups, bring-up procedures, interface behavior, and lessons learned

Requirements

• Requires a Bachelor's degre e in degree in Systems Engineering, Electrical Engineering, Computer Engineering, or a related technical field.
• CLEARANCE REQUIREMENTS: Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
• Bachelor’s degree in Systems Engineering, Electrical Engineering, Computer Engineering, or a related technical field
• Foundational understanding of digital logic, electronics, embedded systems, or hardware/software integration
• Coursework, internship, lab, or project experience with FPGA design, SystemVerilog, VHDL, or FPGA development kits is a plus
• Interest in hardware bring-up, lab debug, payload integration, and hands-on engineering work
• Familiarity with lab equipment such as oscilloscopes, logic analyzers, JTAG, protocol analyzers, or similar tools
• Basic understanding of communication interfaces such as Ethernet, SPI, UART, JESD204, or other board-level protocols
• Comfortable working with software tools, scripts, Linux command-line environments, or Git-based workflows
• Ability to work with multidisciplinary teams and communicate across systems, hardware, software, and test disciplines
• Willingness to learn FPGA toolchains, RTL development, simulation, timing concepts, and hardware integration practices

Skills

Required

• U.S. citizenship